A signal processing device such as a processor, system LSI, and SoC is equipped with a bus monitor circuit that sends bus access information on a main bus inside a chip in an execution mode for the purpose of debugging and external observation outside a chip.
It is preferable that a bus monitor circuit can output bus access information (i.e. an address and control information) paired with data information in an order guaranteeing the occurrence order of bus access. Considering an output clock frequency and the number of external output pins used for externally outputting bus information to the outside of a chip, it is preferable that a large amount of bus access information can be sent using as a small number of bits as possible.
However, when a bus interface protocol enabling pipeline transaction undergoes the concurrent occurrence of a read access and a write access, the actual occurrence order of the read access and the write access may not match the transmitted order of read data (RDAT) and write data (WDAT). In this case, it is difficult to output bus monitor signals indicating bus access information paired with data information.
Due to a recent tendency in a large-scale and high-speed processor system, a bus interface protocol is evolved with an interface specification achieving high-speed access in terms of latency and throughput. In particular, for the sake of improving a throughput in read access, for example, a bus interface protocol enabling pipeline transaction and split transaction such as AMBA3.0AXI and OCP (Open Core Protocol) has been frequently used. In this bus interface protocol supporting pipeline transaction, a command generating order may be reverse to the transmitted order of read data and write data due to the concurrent occurrence of a read access and a write access.
In this case, a bus monitor circuit outputs bus monitor signals in the transmitted order of data information for the purpose of external observation outside a chip, whereas a bus access order is not guaranteed in bus monitor signals. With a bus monitor circuit outputting bus monitor signals that do not guarantee the occurrence order of bus access, it is impossible to obtain bus access information in the actual order of bus access that occurs inside a chip, and therefore it is impossible to conduct debugging with a high efficiency and a high reliability. Due to the nonguaranteed bus access order, it is impossible to provide bus access information paired with data information.
PLT 1 disclosed a technology that concurrently latches addresses, data, and attributes so as to store them in a memory in order to output minimum bus access information in a bus access order. In the technology of PLT 1, in a cycle completely validating an address, data, and an attribute, those elements matching a predetermined bus monitor condition are solely and concurrently latched so that the set of an address, data, and an attribute is stored at the same address in each memory; thus, it is possible to store minimum bus access information in a memory in a bus access order.
PLT 2 disclosed a technology that adopts a plurality of FIFOs to concurrently output bus monitor signals with respect to a plurality of buses. In the technology of PLT 2, a bus access suited to a filtering condition for each bus is solely stored in each FIFO while the stored data of a nonempty FIFO are sequentially outputted; thus, it is possible to efficiently output bus monitor signals with respect to bus access information on a plurality of buses.
PLT 3 disclosed a technology in which an access control circuit of a PCI bus including a write FIFO and a read FIFO is used to minimize nullification of read requests on the PCI bus. To cope with the existence of pending read requests, the technology of PLT 3 prevents or continues a write access using its target address, thus minimizing nullification of read requests.